71. Grams. S. Lin and you may J. B. Kuo, “Fringing-Induced Slim-Channel-Perception (FINCE) Related Capacitance Behavior from Nanometer FD SOI NMOS Products Having fun with Mesa-Isolation Via 3d Simulator” , EDSM , Taiwan ,
72. J. B. Kuo, “Development out of Bootstrap Techniques in Lowest-Current CMOS Digital VLSI Circuits getting SOC Apps” , IWSOC , Banff, Canada ,
P. Yang, “Entrance Misalignment Impression Associated Capacitance Decisions out of a 100nm DG FD SOI NMOS Equipment having n+/p+ Poly Most useful/Bottom Entrance” , ICSICT , Beijing, Asia
73. G. Y. Liu, N. C. Wang and you can J. B. Kuo, “Energy-Successful CMOS High-Stream Driver Routine into the Complementary Adiabatic/Bootstrap (CAB) Technique for Low-Fuel TFT-Liquid crystal display System Software” , ISCAS , Kobe, The japanese ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and K. W. Su, “CGS Capacitance Technology away from 100nm FD SOI CMOS Equipment that have HfO2 High-k Entrance Dielectric Provided Straight and Fringing Displacement Consequences” , HKEDSSC , Hong-kong ,
75. J. B. KUo, C. H. Hsu and you may C. P. Yang, “Gate-Misalignment Associated Capacitance Conclusion out-of a beneficial 100nm DG SOI MOS Gizmos which have Letter+/p+ Top/Bottom Gate” , HKEDSSC , Hong-kong ,
76. G. Y. Liu, N. C. Wang and you may J. B. Kuo, “Energy-Successful CMOS High-Load Rider Circuit toward Complementary Adiabatic/Bootstrap (CAB) Technique for Reduced-Fuel TFT-Lcd System Software” , ISCAS , Kobe, The japanese ,
77. H. P. Chen and J. B. Kuo, “An effective 0.8V CMOS TSPC Adiabatic DCVS Reasoning Circuit with the Bootstrap Approach getting Reasonable-Electricity VLSI” , ICECS , Israel ,
B. Kuo, “A novel 0
80. J. B. Kuo and you can H. P. Chen, “The lowest-Voltage CMOS Weight Driver for the Adiabatic and you can Bootstrap Techniques for Low-Energy System Software” , MWSCAS , Hiroshima, The japanese ,
83. Meters. T. Lin, Age. C. Sunrays, and you will J. B. Kuo, “Asymmetric Door Misalignment Influence on Subthreshold Qualities DG SOI NMOS Products Provided Fringing Electric Field effect” , Electron Devices and you may Issue Symposium ,
84. J. B. Kuo, Age. C. Sunshine, and you may M. T. Lin, “Studies away from Entrance Misalignment Affect brand new Threshold Voltage off Double-Entrance (DG) Ultrathin FD SOI NMOS Products Using a compact Design Given Fringing Digital Field-effect” , IEEE Electron Gizmos for Microwave and Optoelectronic Applications ,
86. E. Shen and you may J. 8V swedish dating site free BP-DTMOS Stuff Addressable Memories Cell Circuit Produced by SOI-DTMOS Process” , IEEE Conference with the Electron Equipment and you may Solid state Circuits , Hong kong ,
87. P. C. Chen and J. B. Kuo, “ic Reasoning Routine Playing with a direct Bootstrap (DB) Technique for Reasonable-voltage CMOS VLSI” , Global Symposium with the Circuits and Expertise ,
89. J. B. Kuo and you can S. C. Lin, “Compact Dysfunction Model for PD SOI NMOS Gizmos Offered BJT/MOS Effect Ionization to possess Liven Circuits Simulation” , IEDMS , Taipei ,
ninety. J. B. Kuo and S. C. Lin, “Compact LDD/FD SOI CMOS Product Model Given Time Transport and you will Notice Heating to own Spice Routine Simulator” , IEDMS , Taipei ,
91. S. C. Lin and you can J. B. Kuo, “Fringing-Induced Hindrance Decreasing (FIBL) Negative effects of 100nm FD SOI NMOS Devices with high Permittivity Gate Dielectrics and LDD/Sidewall Oxide Spacer” , IEEE SOI Appointment Proc , Williamsburg ,
92. J. B. Kuo and you can S. C. Lin, “The fresh Fringing Digital Field-effect to the Short-Station Effect Tolerance Voltage regarding FD SOI NMOS Gizmos with LDD/Sidewall Oxide Spacer Structure” , Hong kong Electron Products Conference ,
93. C. L. Yang and you will J. B. Kuo, “High-Temperatures Quasi-Saturation Make of Large-Current DMOS Energy Devices” , Hong kong Electron Gadgets Appointment ,
94. E. Shen and you may J. B. Kuo, “0.8V CMOS Articles-Addressable-Thoughts (CAM) Telephone Ciurcuit that have an easy Mark-Examine Abilities Having fun with Majority PMOS Vibrant-Endurance (BP-DTMOS) Approach Considering Practical CMOS Tech to have Reduced-Current VLSI Possibilities” , Globally Symposium to the Circuits and Possibilities (ISCAS) Proceedings , Arizona ,